PolyU's 2D TFET Breaks Boltzmann Limit for Energy-Efficient AI Chips

In a groundbreaking development for the semiconductor industry, researchers at The Hong Kong Polytechnic University (PolyU) have engineered a novel tunnelling field-effect transistor (TFET) using 2D nanomaterials, promising to overcome the physical limits that have constrained transistor energy efficiency for decades. This innovation, published in the prestigious journal Science, could pave the way for ultra-low-power, high-performance computing and next-generation AI chips.

Led by Prof. Jianhua Hao, Head of the Department of Physics and Materials and Chair Professor of Materials Physics and Devices at PolyU, the research team collaborated with the National University of Singapore, The Hong Kong University of Science and Technology, Peking University, and the Singapore University of Technology and Design. The team created an ultra-thin heterostructure of alternating layers of 2D bismuth and indium selenide using pulsed laser deposition. By precise control of the layer structure, the normally semi-metallic bismuth transforms into a semiconductor, enabling efficient quantum tunnelling of charge carriers into indium selenide.

The resulting TFET achieves subthreshold swing (SS) values well below the 60 mV/decade limit imposed by the Boltzmann limit, operating at room temperature on silicon substrates. The device requires a gate-voltage range of only 160 mV, compared to the 800 mV originally needed, and delivers a high output current with an exceptionally high ON/OFF current ratio. This breakthrough resolves a longstanding challenge in experimental TFETs, enabling multiple downstream logic gates and reducing circuit delay. The findings, detailed in the Science publication, mark a significant step toward energy-efficient computing and advanced semiconductor applications.